View SC462408_4707235.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

power management sc4624 low input voltage, high effciency, 4a integrated fet synchronous step down dc/dc regulator the sc4624 is a highly integrated synchronous step-down dc/dc regulator designed for low input voltage range of 2.3v to 5.5 volts. it can deliver 4a continuous output current with the output voltage as low as 0.5 volts. the internal low r ds(on) synchronous power switches eliminate the need for external schottky diode while delivering overall converter effciency up to 95%. a power good pin is available to monitor the output voltage status. operating frequency is adjustable from 200 khz to 2mhz with a single resistor and it can be synchronized to an external clock. the sc4624 offers adjustable current limit, soft start and over temperature protection to safeguard the device under extreme operating conditions. the soft start provides a controlled output voltage ramp up at startup. when a logic low is applied to the enable pin, the sc4624 enters the shutdown mode and it consumes less than 1.5a of current. the sc4624 is available in 4x4 mlpq-20 and soic-16edp package, and it is rated over -40c to +105c ambient temperature range. u vin range: 2.3 C 5.5v u 4a continuous output current u adjustable output voltage 0.5v to vin u low r ds(on) integrated fets: 74m and 47m u up to 95% efficiency u synchronizable and programmable frequency: 200khz C 2mhz u power good monitor u <1.5a of shutdown current u programmable soft start u programmable current limit u over temperature protection u -40 to +105c ambient temperature range u starts into pre-biased output u 4x4mm mlpq-20 and soic-16edp packages- weee and rohs compliant u low voltage distributed dc-dc converters u telecommunication power supplies u portable equipment u xdsl www.semtech.com 1 revision: october 08, 2008 description features features typical application circuit applications vout vin r3 r3 c5 c5 c8 c8 r5 r5 r8 r8 r7 r7 r2 r2 c9 c9 c7 c7 c4 c4 r4 r4 c1 c1 r6 r6 c2 c2 r1 r1 r9 r9 sc4624 sc4624 comp fb pgood sync/en vcc ss fs agnd ph iset pvin pgnd c11 c11 r11 r11 c3 c3 l1 l1
2 ? 2008 semtech corp. www.semtech.com power management sc4624 device top mark package sc4624mltrt (1) (2) sc 4624 mlpq-20 sc4624setrt (1) (2) sc4624 so-16 edp sc4624evb-mlpq evaluation board sc4624evb-so notes: (1) available in tape and reel only. a reel contains 3,000 devices for mlpq-20 package and 2,500 devices for so-16 package. (2) available in lead-free package only. device is weee and rohs compliant. ordering information pin confguration 5 5 4 4 3 3 2 2 1 1 d d c c b b a a vcc agnd sync/en pgnd1 pgnd2 ph1 ph2 15 pvin1 fs vcc 6 pgood iset 5 comp ss fb 10 1 11 16 20 nc nc nc ph3 pvin2 top view 20pin mlpq t 5 5 4 4 3 3 2 2 1 1 d d c c b b a a 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 sync/en pgnd1 pgnd2 ph1 ph2 pvin1 pvin2 iset ss fs vcc pgood comp fb vcc agnd top view 16pin soic-edp t ja = 31c/w; jc = 3.9c/w. ja = 29c/w; jc = 2.5c/w.
3 ? 2008 semtech corp. www.semtech.com sc4624 power management absolute maximum ratings absolute maximum ratings absolute maximum ratings exceeding the specifcations below may result in permanent damage to the device, or device malfunction. operation outside of the parameters specifed in the electrical characteristics section is not implied. electrical characteristics unless otherwise specifed, v in = v cc =sync/en=3.3v, r osc =51.1k ?, r iset =27.4k ?, t j = -40c to 125c parameter symbol conditions min typ max units power supply start threshold voltage, uvlo v iuv v in rising 2 2.25 v hysteresis voltage, uvlo v iuvhy 120 mv supply current, shutdown i sd v sync = 0v 0.2 1.5 a parameter symbol conditions min typ max units power supply input voltage operating range v in 2.3 5.5 v ambient temperature range t a -40 105 c junction temperature t j -40 125 c max. output current i outmax 0 4 a recommended operating conditions the performance is not guarantied if exceeding the specifcations below. parameter symbol maximum units supply voltage pv in , v cc -0.3 to 6 v pvin to vcc +/- 0.3 v fb, comp, iset, sync/en, fs, ss, pgood to agnd -0.3 to vcc+ 0.3 v pgnd to agnd +/- 0.3 v phase voltage to pgnd v phase -0.3 to pvin+ 0.3 v phase pulse voltage to pgnd tpulse < 50ns v phase -3 to pvin+ 2 v storage temperature range t stg -65 to 150 c junction temperature t j 150 c ir refow temperature t p 260 c lead temperature (soldering) 10 sec for so package only t lead 300 c esd protection level (1) v esd 2 kv note: 1) tested in accordance to jedec standard jesd22-a114b.
4 ? 2008 semtech corp. www.semtech.com power management sc4624 electrical characteristics (cont.) unless otherwise specifed, v in = v cc =sync/en=3.3v, r osc =51.1k ?, r iset =27.4k ?, t j = -40c to 125c. parameter symbol conditions min typ max units power supply (cont.) supply current, operating i qswitching fb = comp, no load 7 10 ma i ql fb = 0.6v, no load 3.5 7 ma thermal shutdown thermal shutdown trip point t otp temperature rising 160 c thermal shutdown hysteresis t otp_hys 10 c synchronization, enable input sync/en threshold v enl logic low 0.8 v v enh logic high 2.0 v frequency range, sync f sync 20% higher than f osc 200 2000 khz oscillator osciilator frequency range f osc 200 2000 khz osciilator frequency accuracy r osc = 51.1k? 415 500 600 khz r osc =51.1k?, t a =t j =25c 435 500 565 khz ramp peak to valley (1) v pv 1.0 v ramp peak voltage (1) v p 1.25 v ramp valley voltage (1) v v 0.25 v soft start, current limit soft-start charge current i ss 4 a iset bias voltage v iset r iset = 27.4k? 0.45 0.55 0.62 v over current trip i ist r isit = 57.6k? 1.9 2.55 3.1 a output uvlo v ouv vfb drop 0.3 v hiccup period (1) t ochp 131072 clks error amplifer error amplifer open loop voltage gain (1) 100 db error amplifer unity gain bandwidth (1) 10 mhz output voltage slew rate, comp (1) 4 v/s
5 ? 2008 semtech corp. www.semtech.com sc4624 power management electrical characteristics (cont.) unless otherwise specifed, v in = v cc =sync/en=3.3v, r osc =51.1k ?, r iset =27.4k ?, t j = -40c to 125c. parameter symbol conditions min typ max units error amplifer (cont.) source output current, comp fb = 0.4v 20 ma sink output current, comp fb = 0.6v 25 ma output voltage high, comp fb = 0.4v, i comp = -1ma 2.5 v output voltage low, comp fb = 0.6v, i comp = 1ma 0.1 0.25 v feedback voltage v fb 0.4925 0.5 0.5075 v vcc = 2.3v to 5.5v -2 + 1 +2 % input bias current (1) i fb fb=v ref 300 na power switches high-side p-mosfet r dsh(on) v in =v cc =5v, i source = 1a, t a =t j =25 c 74 100 m? low side n-mosfet r dsl(on) v in =v cc =5v, i sink = 1a, t a =t j =25 c 47 85 m? power good pgood voltage low v pgl i pgood = 1ma 0.2 v pgood leakage current i pgood pgood = 5v 1 a pgood delay time (1) t d vout rising or vout falling 1024 clks pgood high window with respect to nominal output, t a =t j =25 c + 8 + 10 + 15 % note: (1) guaranteed by design.
6 ? 2008 semtech corp. www.semtech.com power management sc4624 operation typical performance characteristics typical performance characteristics figure 3. shutdown by v in @0a figure 4. shutdown by v in @4a figure 5. transient response@ 0 to 4a figure 6. ripple and stability@4a figure 1. start up by v in @0a figure 2. start up by v in @4a circuit condition: application circuit#1, 5v in , 1v out vin vout start up by vin test condition: 5vin, 1vo, io=0a pgood ss v in ss v out pgood 5v/div 5v/div 5v/div 0.5v/div 10ms/div 5v/div 5v/div 0.5v/div 5v/div vin vout start up by vin test condition: 5vin, 1vo, io=0a pgood ss v in ss v out pgood 10ms/div vin vout shutdown by vin test condition: 5vin, 1vo, io=0a pgood ss 5v/div 5v/div 5v/div 0.5v/div v in ss v out pgood 5ms/div vin vout shutdown by vin test condition: 5vin, 1vo, io=4a pgood ss 5v/div 5v/div 5v/div 0.5v/div v in ss v out pgood 1ms/div transient response test condition: 5vin, 1vo, io=0 to 4a r=f=2.5a/us,t1=t2=0.1ms io vout vout iout v out l out 2a/div 50mv/div 20us/div v out v phase 20mv/div 2.0v/div stability and ripple vphase vout test condition: 5vin, 1vo, io=4a, (operating stably) 1us/div
7 ? 2008 semtech corp. www.semtech.com sc4624 power management operation typical performance characteristics (cont.) typical performance characteristics (cont.) figure 11. high-side p-mosfet figure 12. low-side n-mosfet figure 7. over load hiccup figure 9. synchronization figure 10. effciency(v in ) v out ss v phase figure 8. thermal shutdown protection@0a v out ss v phase sync signal v phase output current(a) 70 80 90 100 110 120 130 1 2 3 4 2 . 5 v in 3 . 3 v in 5 v in r dson (m ? ) i out (a) internal pmos r dson @ room temperature internal nmos r dson @ room temperature 50 55 60 65 70 75 80 1 2 3 4 2 . 5 v in 3 . 3 v in 5 v in r dson (m ? ) i out (a) 5.0v/div 3.0v/div 0.6v/div 2.0v/div 2.0v/div 0.6v/div 3v/div 5.0v/div test condition: 5vin, 1vout ss vphase over current protection vout 100ms/div circuit condition: application circuit#1, 5v in , 1v out test condition: 5vin, 1vout ss vphase thermal protection vout 1s/div efficiency ?? ? ? ? ? ?? ? ? ??? ?? ? ?? ? ?? ? ?? ? ?? a3????? ??????? 5vin 3.3vin 2.5vin (iflhqf sync sync vphase 1us/div (whuqdoforfnvlqjdo n+gw
8 ? 2008 semtech corp. www.semtech.com power management sc4624 operation typical performance characteristics (cont.) typical performance characteristics (cont.) figure 13. loading regulation figure 14. over current setting versus r iset 2.36 2.38 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 vout regulation during switching to linear mode v out (v) i out (a) i out (a) r iset (k?) ocp trip ????e????3? ?? ?? ? ?? ?? ?? ?? ? ?? ?? ?? ?? ? ?? ? ?? ? ? ? ? ?? ? ? ??? ?????t?? a??? 3.3vin 5vin 2.5vin
9 ? 2008 semtech corp. www.semtech.com sc4624 power management pin descriptions pin so-16 pin mlpq-20 pin name pin functions 6 1 pvin1 power supply voltage for high side mosfets. 8 2 iset current limit setting pin. a resistor connected between iset and agnd sets the over current protection threshold. a ceramic decoupling between iset pin to agnd have to be reserved to prevent from noise infuence. 9 3 ss soft start time setting pin. a cap connected from this pin to gnd sets the soft start up time. 10 4 fs oscillator frequency setting pin. an external resistor connected from this pin to gnd sets the oscillator frequency. 11,15 5,12 vcc power supply voltage for the analog section of the controller. 12 6 pgood power good indicator. it is an open drain output. low when the output is below the power good threshold level. 7,8,9 nc no connection. 13 10 comp this is the output of the error amplifer. the voltage at this point is connected to the inverting input of the pwm comparator. a compensation network is required in order to optimize the dynamic performance of the voltage mode control loop. 14 11 fb the inverting input of the error amplifer. it serves as the output voltage feedback point for the buck controller. it senses the output voltage through an external divider. 16 13 agnd analog signal gound. 1 14 sync/en the oscillator frequency of the sc4624 is set by fs when sync/en is pulled and held above 2v. its synchronous mode is activated as sync/en is driven by an exter - nal clock. its shutdown mode is invoked if sync/en is pulled and held below 0.8v . 2 15 pgnd1 power ground. 3 16 pgnd2 power ground. 4 17 ph1 switching nodes 5 18 ph2 switching nodes 19 ph3 switching nodes 7 20 pvin2 power supply voltage for high side mosfets. thermal pad pad for heatsinking purposes only. connect to ground plane using multiple vias. not electrically connected internally.
10 ? 2008 semtech corp. www.semtech.com power management sc4624 block diagram agnd vcc ss fb comp sync / en fb bandgap bandgap vref soft start osc clock sd pwm block pwm logic error opamp shoot - thru protection thermal shutdown uvlo c o n t r o l a n d h i c c u p + - 0 . 5 v + - over current protect bottom gate low side driver and logic 1 . 1 vref 0 . 9 vref pgood pgnd 2 pgnd 1 ph 3 ph 2 ph 1 iset pvin 2 pvin 1 i = f ( r _ iset ) high side driver and logic top gate d e l a y asynchronous start up fs
11 ? 2008 semtech corp. www.semtech.com sc4624 power management application information overview the sc4624 is a programmable high switching frequency, integrated 4a mosfet, synchronous step down regulator. this reduces external component count and makes it effective for applications which are low in cost and sized small. a non-overlap protection is provided for the gate drive signals to prevent shoot through of the internal mosfet pair. the sc4624 is capable of producing an output voltage as low as 0.5v and its operation frequency is programmable up to 2mhz by an external resistor. it features lossless current sensing of the voltage drop across the internal drain to source resistance of the high side mosfet during its conduction period. the quiescent supply current in shutdown mode is typically lower than 1a. an external soft start is provided to prevent output voltage overshoot during start-up. over temperature protection, power good indicator, external clock synchronization are some of the internal added features. enable the sc4624 is enabled by applying a voltage greater than 2v (typical) to the v cc and sync/en pin. the voltage on the v cc pin determines the operation of the sc4624. as v cc increases during start up, the uvlo block senses v cc and keeps the high side and low side mosfets off and the internal soft start voltage low until v cc reaches 2v. if no faults are present, the sc4624 will initiate a soft start when v cc exceeds 2v. a typical 120mv hysteresis in the uvlo comparator provides noise immunity during its start up. (refer to figure 1 to 2). shutdown the sc4624 is disabled when v cc falls below 1.88v (typical) or shutdown mode operation is invoked by clamping the sync/en pin to a voltage below 0.8v. during the shutdown mode, a typical 0.2a current draw through the v cc pin, the internal soft start voltage is held low and the internal mosfets are turned off. (refer to figure 3 to 4). soft start the soft start function is required for step down controllers to prevent excess in-rush current through the dc bus during start up. an external capacitor is necessary for the soft start function and is connected from ss pin to agnd. during start up or restart, a typical 4a sourcing current charges the capacitor and then the voltage of capacitor ramp up the error amp reference slowly. the closed loop creates narrow width driver pulses while the output voltage is low and allows these pulses to increase to their steady state duty cycle as the output voltage reaches its regulated value. the duration of the soft start in the sc4624 is controlled by an external capacitor. the sc4624 starts up in asynchronous mode before ss voltage reaches to 0.5v, and the bottom fet diode is used for circulating current during the top fet off time. ths ss voltage level is clamped at v cc fnally. pre-biased output the sc4624 is able to start into pre-biased output by adding external rc circuit, where r(10k ? ) is between v cc pin and en pin, c(0.1uf) is between en pin and agnd. if there is a pre-biased load on the output of sc4624 during start-up, the internal low-side mosfet of sc4624 is always disabled before ss reach to 0.5v, the output voltage is maintained. the great feature avoids negative voltage spikes or short circuit on the output, which could cause damage to the down-stream ic during start-up. timing between v cc and en is very important for pre-biased output. v cc must lead en. when v cc and en voltage rise at same time(tied together), the pre-biased output voltage is pull low before v cc reach to the voltage of uvlo. if this isnt desirable, rc(10k ? and 0.1uf) must be added at en to prevent this from happening. oscillator the fs pin is used to set the pwm oscillator frequency through an external resistor that is connected from the fs pin to the agnd. the internal ramp is a triangle at the pwm frequency with a peak voltage of 1.25v and a valley voltage of 0.25v. the approximate operating frequency is determined by the value of an external resistor as shown in figure 15.
12 ? 2008 semtech corp. www.semtech.com power management sc4624 operation application information (cont.) application information (cont.) 5 15 25 35 45 55 65 75 85 95 105 115 125 135 145 200 400 600 800 1000 1200 1400 1600 1800 2000 5 vin 2 . 5 vin the operation frequency can be programmed up to 2mhz, but there is a minimum on-time limitation which is around 110ns. users should take care of minimum limitation on the operating duty cycle under high frequency application. synchronization frequency synchronization operation mode is invoked by using an external clock signal and is activated when the sync/en is pulled and held above 2v and held below 0.8v. the range of synchronization frequency is from 200khz to 2mhz. a jitter happens when sync pulse clock edge is less than 120ns before the phase switches. it is caused by the ground bounce of synchronization pulse coupled to pwm comparator. users try to avoid this application. (refer to figure 9). power good indicator the pgood pin is an open-drain and incorporated window comparators output. its is necessary that a pull-up resistor from the pgood pin to the input supply for setting the logic high level of the pgood signal. when fb voltage is within + 10% setting output voltages typical, the output of power good comparator becomes high impedance after delay time. the pgood signal delay time is around 1024/ f osc . in shutdown mode the power good output is actively pulled low. for example, 1mhz switching frequency applications, the pgood delay time is around 1ms. thermal shutdown when the junction temperature rises up around 160c, the internal soft start voltage is held low, the internal high side and low side mosfets are turned off and the output voltage will fall to zero. once the junction temperature goes below hysteresis temperature around 10c, the regulator will restart. (refer to figure 8). linear mode operation (100% duty) the sc4624 can allows 100% duty cycle operation. the vout is, 28 7 '6 + / ,1 28 7 , 5 5 9 9 u where r l : output inductor dc resistance. r dsh : internal high side p-mosfet resistance. (refer to figure11). as vin drops gradually and close to vout, the buck regulator will go into 100% duty cycle ratio. a matter needing attention is internal high side pmos has minimum off time limitation and is related to duty cycle rate. t his condition makes the working duty cycle perform at randon with the output ripple increasing and a poor transient response. above phenomenon can be improved by larger output capacitor and smaller output inductor. users need to verify whether above application condition has opposite infuence on entire circuit. over current protection a over current setting is programmed by an external resistor (r iset ). it goes through internal sense resistor and generates a voltage. 2qvhqv h ff 5 , 9 9 u where i : the current is generated by r iset , and it is amplifed by internal current amplifer. r onsense : internal sense resistor. output inductor current goes through internal high side p-mosfet and generate a voltage. 21 '6 + / ,1 5 , 9 9 u where i l : output inductor current. r dsh(on) : high side p-mosfet conduction resistance. r fs (k?) switching frequency setting f osc (khz) figure 15. switching frequency vs. r fs
13 ? 2008 semtech corp. www.semtech.com sc4624 power management application information (cont.) after the high side pmos turn on around 30ns, the ocp comparator will compare between v2 and v1. when the converter detects an over current condition (v2 > v1) as shown in figure 16, the sc4624 proceeds into the cycle by cycle protection mode (point b to point c), which responds to minor over current cases and the output voltage is monitored. if the over current and low output voltage (set at 60% of nominal output voltage) occur at the same time, the ss pin is pull low by an internal switch and the comp pin is pulled low and the devices stops switching. assume start from fb = 0v, fb and ss voltage rise forward 0.5v. once ss voltage exceeds 0.4v, the hiccup comparator becomes enabled. the hiccup period is around 2 17 /f osc . (point c to point d). for example, with a switching frequency application of 550khz, the hiccup period is around 238ms. (refer to figure 7). a poor layout will make ocp trip point shift and is not easily to calculate by r iset . this is because it is affected by ground bounce, spiker voltage between vin pin and ph pin, and internal parameter tolerance. users can refer to figure 14, it shows how to set maximum output current by r iset . c d iout 0 imax vout 0 . 6 * vout vo a 0 b figure 16. over current protection characteristic inductor selection for a typical sc4624 application, the inductor selection is mainly based on its value, saturation current and dc resistance. the inductor should be able to handle the peak current without saturating and its copper resistance in the winding should be as low as possible to minimize its resistive power loss. the inductor value can be determined according to its operating point and the switching frequency as follows: 20$; 6 ,1 28 7 ,1 28 7 , , i 9 9 9 9 / u ' u u u where fs = switching frequency. d i = ratio of the peak to peak inductor current to the maximum output load current. the peak to peak inductor current is: 20$; 3 3 , , , u ' after the required inductor value is selected, the proper selection of the core material is based on the peak inductor current and effciency requirements. the core must be able to handle the peak inductor current i peak without saturation and produce low core loss during the high frequency operation and is given as follows: , , , 3 3 ,20$ ; 3($. the power loss for the inductor includes its core loss and copper loss. if possible, the winding resistance should be minimized to reduce any copper loss of the inductor, (the core loss can be found in the manufacturers datasheet). the inductors copper loss can be estimated as follows: :,1',1 * /506 &223(5 5 , 3 u where i lrms is the rms current in the inductor. this current can be calculated as follows: 20$; /506 , , , ' u u output capacitor selection basically there are two major factors to consider in select - ing the type and quantity of the output capacitors. the frst one is the required esr (equivalent series resis - tance) which should be low enough to reduce the voltage deviation from its nominal one during its load changes. the second one is the required capacitance, which should be high enough to hold up the output voltage. before the
14 ? 2008 semtech corp. www.semtech.com power management sc4624 sc4624 regulates the inductor current to a new value dur - ing a load transient, the output capacitor delivers all the additional current needed by the load. the esr and esl of the output capacitor, the loop para - sitic inductance between the output capacitor and the load combined with inductor ripple current are all major contributors to the output voltage ripple. input capacitor selection the input capacitor selection is based on its ripple cur - rent level, required capacitance and voltage rating. this capacitor must be able to provide the ripple current by the switching actions. for the continuous conduction mode, the rms value of the input capacitor can be calculated from: ,1 9 9 9 9 , , 28 7 ,1 28 7 20$; 50 6 &, 1 u u this current gives the capacitors power loss as follows: (6 5 &, 1 50 6 &, 1 &, 1 5 , 3 u this capacitors rms loss can be a signifcant part of the total loss in the converter and reduces the overall convert - er effciency. the input ripple voltage mainly depends on the input capacitors esr and its capacitance for a given load, input voltage and output voltage. assuming that the input current of the converter is constant, the required input capacitance for a given voltage ripple can be calcu - lated by: (6 5 &, 1 20$; , 6 20$; ,1 5 , '9 i ' ' , & u u u u where d = v o /v i , duty ratio. d v i = the given input voltage ripple. loop compensation design for a dc/dc converter, it is usually required that the con - verter has a loop gain of a high cross-over frequency for fast load response, high dc and low frequency gain for low steady state error, and enough phase margin for its oper - ating stability. often one can not have all these properties at the same time. the purpose of the loop compensation is to arrange the poles and zeros of the compensation operation application information (cont.) application information (cont.) network to meet the requirements for a specifc applica - tion. the sc4624 has an internal error amplifer and requires the compensation network to connect among the comp pin and fb pin, gnd, and the output as shown in figure 17. the compensation network includes c1, c2, r1, r7, r8 and c8. r9 is used to program the output voltage ac - cording to: 5 5 9 2 u 5 5 4 4 3 3 2 2 1 1 d d c c b b a a r7 r1 c4 c1 l1 r c2 sc4624 comp fb ph r9 c8 r8 vout figure 17. compensation network provides 3 poles and 2 zeros for voltage mode step down applications as shown in fig - ure 17, the power stage transfer function is: where r = load resistance r c = c4s esr. the compensation network will have these characteris - tics: in ? 2 p 2 z 1 p 1 z i comp s 1 s 1 s 1 s 1 s ) s ( g w + ? w + ? w + w + ? w =
15 ? 2008 semtech corp. www.semtech.com sc4624 power management operation application information (cont.) application information (cont.) where ) c c ( r 1 2 1 7 i + ? = 2 1 1 z c r 1 ? = 8 8 7 2 z c ) r r ( 1 ? + = 2 1 1 2 1 1 p c c r c c ? ? + = 9 8 2 p c r 1 ? = after the compensation, the converter will have the following loop gain: = where g pwm = pwm gain. v m = 1.0v, ramp peak to valley voltage of sc4624. the design guidelines for the sc4624 applications are as follows: set the loop gain crossover corner frequency w c for given switching corner frequency w s = 2 p fs, place an integrator at the origin to increase dc and low frequency gains. select w z1 and w z2 such that they are placed near w o to damp the peaking and the loop gain has a -20db/ dec rate to go across the 0db line for obtaining a wide bandwidth. cancel the zero from c4s esr by a compensator pole w p1 ( w p1 = w esr = 1/(r c c 4 )). place a high frequency compensator pole w p2 ( w p2 = p fs) to get the maximum attenuation of the switch - ing ripple and high frequency noise with the adequate phase lag at w c . the compensated loop gain will be as given as show in figure 18. figure 18. asymptotic diagrams of power stage and loop gain 1. 2. 3. 4. 5. c l s r l s 1 c r 1 s 1 s 1 s 1 s 1 s 1 s v v 1 ) s ( g ) s ( g g ) s ( t 1 2 1 4 c 2 p 2 z 1 p 1 z i i m vd comp pwm + + ? + ? w + ? w + ? w + w + ? ? w ? = ? ? = 8 c l s r l s 1 c r 1 s 1 s 1 s 1 s 1 s 1 s v v 1 ) s ( g ) s ( g g ) s ( t 1 2 1 4 c 2 p 2 z 1 p 1 z i i m vd comp pwm + + ? + ? w + ? w + ? w + w + ? ? w ? = ? ? =
16 ? 2008 semtech corp. www.semtech.com power management sc4624 operation application information (cont.) application information (cont.) layout guidelines in order to achieve optimal thermal and noise immunity for high frequency converters, special attention must be paid to the pcb layout. the goal of layout optimization is to minimize the high di/dt loops and reduce ground bounce. output voltage setting, line regulation, stability , switching frequency and ocp trip point shifted are affected by a poor layout. the following guidelines should be used to ensure proper functions of the converters. both power ground (pgnd) and signal ground (agnd) are separated. a ground plane is recommended to minimize noise and copper losses, and maximize heat dissipation. start the pcb layout by placing the power components frst. arrange the power circuit to achieve a clean power fow route. minimize all high di/dt loops. these loops pass high di/dt current. make sure the trace width is wide enough to reduce copper losses in this loop. ground bounce happen to magnetic fux changed and it is proportional to a magnetic fled which goes through high di/dt loops. the input ceramic capacitor (c in ) should be close to pv in pins and pgnd pins. both input ceramic capacitor gnd and output ceramic capacitor gnd are at same port. a rc snubber circuit between pv in and ph pins is helpful for stability operation. be careful with power derating of snubber circuit. the v cc bypass capacitor should be placed next to the v cc and agnd pins. the ocp setting resistor (r iset ) and flter capacitor (c iset ) should be placed next to the iset and agnd pins. feedback divider connects to output connector by kelvin connection and far away from the noise sources such as switching node and switching components. a multilayer chip beads between agnd and pgnd will reduce the ground bounce injected to the quiet circuit. its helpful for stability operation. a large copper area underneath the sc4624 ic is necessary for heat sinking purpose. and multiple layers of large copper area connected through vias can be used for better thermal performance. the size of the vias as the connection between multiple layers should not be too large or solder may seep through 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. the big vias to the bottom layer during the re-fow process .
17 ? 2008 semtech corp. www.semtech.com sc4624 power management operation application information (cont.) application information (cont.) 5v in , 1v out , 4a, all ceramic capacitors ( application circuit#1 ) 5 5 4 4 3 3 2 2 1 1 d d c c b b a a 5vin 1vout@4a title size document number rev date: sheet of a2 custom 1 1 monday, june 25, 2007 title size document number rev date: sheet of a2 custom 1 1 monday, june 25, 2007 title size document number rev date: sheet of a2 custom 1 1 monday, june 25, 2007 sc4624 application circuit vin=5v; vout=1v/4a input(c9)/output capacitors(c4): panasonic ecj33ybo j226m(22uf/6.3v) l1: toko d104c(919as-1r8n) switching frequency=550khz r12: multilayer chip inductors; mlb-160808-0600r-s 2 (1) (2) note: (1,2) option for stability r9 28.7k r9 28.7k r11 47.5k r11 47.5k c5 opt c5 opt c3 1uf c3 1uf c8 270pf c8 270pf r6 10k r6 10k u1 sc4624 u1 sc4624 comp 10 fb 11 pgood 6 sync/en 14 vcc 5 ss 3 nc 9 nc 7 fs 4 agnd 13 vcc 12 ph1 17 ph2 18 ph3 19 nc 8 iset 2 pvin1 1 pvin2 20 pgnd1 15 pgnd2 16 pad c11 opt c11 opt r2 10r r2 10r c7 47nf c7 47nf r12 mlb-160808-0600r-s2 r12 mlb-160808-0600r-s2 r1 20k r1 20k c9 22uf c9 22uf r8 2.32k r8 2.32k c2 390pf c2 390pf r7 28.7k r7 28.7k r5 10k r5 10k c1 2.2pf c1 2.2pf c4 22uf c4 22uf r4 opt r4 opt c6 1nf c6 1nf r3 30k r3 30k l1 1.8uh l1 1.8uh
18 ? 2008 semtech corp. www.semtech.com power management sc4624 operation pcb layout pcb layout component side (top) (top layer) (bottom layer) (in1 layer) (in2 layer)
19 ? 2008 semtech corp. www.semtech.com sc4624 power management outline drawing - mlpq - 20 dimensions k h g z x p (c) company's manufacturing guidelines are met. 4.80 .189 z y failure to do so may compromise the thermal and/or thermal vias in the land pattern of the exposed pad shall be connected to a system ground plane. functional performance of the device. 2. this land pattern is for reference purposes only. consult your manufacturing group to ensure your notes: 1. dim x y h k p c g millimeters inches (3.95) .010 .033 .122 .020 .106 .106 (.156) 0.25 0.85 2.70 0.50 2.70 3.10 land pattern - mlpq - 20 bxn bbb c a b d1 e1 e d/2 .001 max .002 - .039 nom 0.80 0.02 (0.20) 0.90 controlling dimensions are in millimeters (angles in degrees). coplanarity applies to the exposed pad as well as the terminals. notes: 2. 1. 1 2 n e1 .100 .106 .110 2.55 2.70 2.80 pin 1 indicator 4.10 3.90 4.00 4.10 3.90 .157 .154 .161 .154 .161 aaa c a c (laser mark) d e b a1 a a2 seating plane lxn e/2 inches .020 bsc b .007 bbb aaa n d1 e l e d .012 .100 dim a1 a2 a min .000 - .031 0.30 0.18 .012 0.25 .010 0.50 2.80 0.30 2.55 .004 .004 20 .016 .157 .106 .020 .110 0.10 0.10 20 0.40 4.00 2.70 0.50 bsc millimeters max 0.05 - 1.00 dimensions min 0.00 - nom (.008) .035
20 ? 2008 semtech corp. www.semtech.com power management sc4624 outline drawing - so-16 edp land pattern - so-16 edp this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. reference ipc-sm-782a, rlp no. 300a. 2. inches dimensions z p y x dim c f millimeters .094 2.40 3. thermal vias in the land pattern of the exposed pad shall be connected to a system ground plane. failure to do so may compromise the thermal and/or functional performance of the device. (c) p x g y z f d (.205) (5.20) 1.27 .050 0.60 .024 2.20 .087 7.40 .291 e solder mask thermal via ? 0.36mm d 2.90 .114 e .201 5.10 g .118 3.00 semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 contact information www.semtech.co m 1 2 n e a 2x e/2 e1 e d ccc c 2x n/2 tips e/2 b f dim c e h l e1 e d a1 a2 b a ccc aaa bbb 01 n l1 datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). dimensions "e1" and "d" do not include mold flash, protrusions plane gauge 0.25 see detail reference jedec std ms-012, variation ac. or gate burrs. 4. 3. notes: 2. 1. -a- -b- side view 0.10 .004 -h- 01 (l1) l detail a a .008 .010 h c 0.20 0.25 millimeters min 6.00 bsc 1.27 bsc .005 0.00 .000 - .105 .028 (.041) .390 .154 .236 bsc .050 bsc .100 .010 .016 0 16 - - .049 .007 .012 .386 .150 - - - .110 .020 .041 8 0.40 0 2.54 0.25 .065 .010 .020 .394 .157 9.80 3.80 1.25 0.17 0.31 inches dimensions nom min .053 - max .069 1.35 0.13 - (1.04) 0.72 16 - 2.67 - 1.04 8 2.79 0.50 9.90 3.90 - - - 10.00 4.00 1.65 0.25 0.51 max nom - 1.75 plane seating c aaa c a a1 a2 bbb c a-b d d bxn exposed pad f h h h h .080 .085 .090 2.03 2.16 2.29 3

▲Up To Search▲

Price & Availability of SC462408

	To Download SC462408 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .